1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device, and particularly, to a design method of arrangements and shapes of various kinds of alignment marks for use in manufacturing processes of the semiconductor device, and to a design system thereof.
2. Description of the Related Art
A semiconductor integrated circuit has a multilayered structure, and in manufacturing processes thereof, it is necessary that the semiconductor integrated circuit undergo no less than several ten lithography processes. In the lithography processes, positioning of each mask during exposure is performed by use of alignment marks in order to accurately align device patterns of lower layers and device patterns of upper layers. Moreover, in an alignment error test between the respective layers, marks for measuring errors, which are different from the alignment marks, are used. Furthermore, besides the marks for the lithography processes, marks for aligning a testing apparatus and a correction apparatus are also used. As described above, in the respective manufacturing processes of a semiconductor device, various kinds of marks in accordance with the respective processes are used. In addition, it is necessary that these marks be arranged in areas on the masks, where the device patterns are not formed, and arrangements of the marks are left to designers.
Regarding the alignment marks, manufacturers of exposure apparatuses and the others recommend use of alignment marks of specific shapes and sizes, and many manufacturers of semiconductors have mainly used these recommended alignment marks. However, actually, due to influences of substrate structures to be subjected to the lithography, process conditions, pattern densities of devices to be formed or the like, these alignment marks are not always suitable for the individual manufacturing processes in many cases. In this connection, actually, persons in charge of the respective manufacturing processes modify the alignment marks as appropriate for use.
However, it becomes more necessary to select the optimal marks for use in consideration of the influences of the process conditions and the like because a higher accuracy has come to be required also for the alignment as densities of LSI patterns have become higher.
Accordingly, for example, with regard to alignment marks for registering specific two layers, work has come to be performed, in which many kinds of marks for alignment and many kinds of marks for measuring alignment errors are prepared in advance, and after undergoing the actual semiconductor processes, the optimal marks for the concerned process are selected. This is because detection and measurement accuracies for the marks are changed due to differences between the shapes and dimensions of the marks.
However, when many marks are arranged on a wafer, if layers to be adjusted for alignment are increased in an area where the marks can be arranged, it is a burden for designers of an LSI to eliminate a contradiction between the mark arrangements in the previous and following processes.
Moreover, when the kind and number of marks are increased, in some cases, it becomes impossible to arrange all of the marks to be arranged on the wafer because the area where the marks can be arranged is limited.
Furthermore, a simulation of mark detection signals is sometimes performed when the optimal marks are to be selected based on a contrast of the mark detection signals. In many cases, the processes are actually performed, and the simulation is performed only for marks causing problems, and the shape of the masks is redesigned. However, cost required for the redesign has become a large burden.
Accordingly, it is desired to provide the optimal marks to respective manufacturing processes efficiently by performing a simulation regarding a mark design in advance without actually undergoing the processes. Moreover, it is desired a semiconductor manufacturing method that has a high accuracy and is capable of reducing cost by use of the foregoing mark design method.